1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of semiconductor elements isolated by dielectric isolation and relates to a method of manufacturing the same.
2. Description of the Background Art
FIG. 1 is a sectional view showing a conventional semiconductor device of an isolation type composite element structure which has a plurality of semiconductor elements isolated by dielectric isolation. As shown in FIG. 1, the semiconductor device comprises an insulation gate type field effect transistor 10A and a junction type bipolar transistor 10B on the upper portion of an n.sup.- polysilicon substrate 1. The transistors 10A, 10B are isolated by an insulation film 2 from each other. A prescribed thickness of n.sup.+ layer 3 is formed on the insulation film 2, and an n.sup.- layer 4 is formed on the n.sup.+ layer 3.
In a region for element formation (referred to as an "island" below) in which the field effect transistor 10A is formed, a p type well region 5 is formed on the upper portion of the n.sup.- layer 4. An n.sup.+ source region 6 is selectively formed on the upper surface of the p type well region 5.
On the upper surface of the p type well region 5 between the surfaces of the n.sup.- layer 4 and n.sup.+ source region 6, polysilicon gates 8 are formed with gate oxide film 7 interposed therebetween. Drain electrodes 9 are formed on the surfaces of the n.sup.+ layer 3. A source electrode 11 is formed on parts of the surfaces of the n.sup.+ source regions 6 and the surface of the p type well region 5 between the n.sup.+ source regions 6. Gate electrodes 12 are formed on the polysilicon gate 8. These electrodes 9, 11 and 12 are insulated from each other by a passivation film 18.
In an island of the bipolar transistor 10B, a p type base region 13 is formed on the upper portion of the n.sup.- layer 4. An n.sup.+ emitter region 14 is formed on a part of the surface of the p type base region 13. An emitter electrode 15 is formed on the n.sup.+ emitter region 14. A base electrode 16 is formed on the p type base region 13. A collector electrode 17 is formed on the n.sup.+ layer 3. These electrodes 15 to 17 are insulated from each other by a passivation film 18.
FIGS. 2A to 2F are sectional views showing steps for manufacturing islands in the semiconductor device shown in FIG. 1. The manufacturing steps will be described with reference to these figures.
An oxide layer 22 is deposited on the surface of an n.sup.- substrate 21 of monocrystal and patterned as shown in FIG. 2A. The n.sup.- substrate 21 is anisotropically etched to form V-shaped grooves 23 by using the patterned resist layer 22 as a mask, as shown in FIG. 2B. A distance l between grooves 23 defines a width of each island.
After removing the oxide film 22, n-type impurities are diffused on the surfaces of the n.sup.- substrate 21 as well as the grooves 23 to form an n.sup.+ layer 3 as shown in FIG. 2C. The n.sup.+ layer 3 is treated with hydrofluoric acid contained chemical (e.g., a phosphorous glass layer or the like is removed from the surface of the n.sup.+ layer 3) in a pretreatment, and then an insulation film 2 such as a thermal oxide film is formed on the n.sup.+ layer 3 as shown in FIG. 2D.
An n.sup.- polysilicon layer 24 is deposited on the insulation film 2 by epitaxial growth technology as shown in FIG. 2E. Then, the bottom surface of the n.sup.- substrate 21 is polished to expose the insulation film 2 and the n.sup.+ layer 3 on the bottom surface of the n.sup.- substrate 21.
Turning the n.sup.- substrate 21 upside down results in a plurality of islands 25 shown in FIG. 2F. The n.sup.- polysilicon layer 24 corresponds to the n.sup.- polysilicon substrate 1 in FIG. 1. Remaining parts of the n.sup.- substrate 21 corresponds to the n.sup.- layer 4 in FIG. 1. The islands 25 are insulated from each other by the insulation film 2. The field effect transistor 10A and the bipolar transistor 10B shown in FIG. 1 are formed in the islands 25 thus obtained.
When the source electrode 11 of the field effect transistor 10A is set at a prescribed potential and a prescribed voltage is applied to the gate electrode 12, a channel region 5a, which is defined in the surface of the p type well region 5 under the polysilicon gate 8, is inverted into an n type to form a channel. As a result, the field effect transistor 10A becomes conductive, so that the drain current flows across the drain electrode 9 and the source electrode 11.
An ON-state resistance is the sum mainly of resistance on the channel region 5a and resistance on the n.sup.- layer 4. The resistance on the n.sup.- layer 4 is increased in proportion to the width of the n.sup.- layer 4 (the distance from the n.sup.+ layer 3 to the p type well region 5) if resistivity is the same throughout the n.sup.- layer 4. Accordingly, the thickness of the n.sup.- layer 4 must be decreased so as to reduce the value of the ON-state resistance.
On the other hand, the thicker the n.sup.- layer 4 is, the wider a depletion layer can extend when resistivity is the same throughout the n.sup.- layer 4. Therefore, the thicker the width of the n.sup.- layer 4 is, the higher the breakdown voltage of the field effect transistor 10A becomes. Accordingly, the thickness of the n.sup.- layer 4 must be increased so as to enhance the breakdown voltage of the field effect transistor 10A.
Thus, it should be noted that the thickness of the n.sup.- layer 4 of the field effect transistor 10A must be optimum because it affects the field effect transistor 10A with regard to an electrical characteristic such as an ON-state resistance, breakdown voltage or the like. As to the bipolar transistor 10B, the thickness of the n.sup.- layer 4 must be optimum in view of reducing collector-to-emitter saturation voltage as much as possible and obtaining sufficient breakdown voltage, similarly to the field effect transistor 10A.
Accordingly, it is desired that the thickness of the n.sup.- layer 4 of each of the field effect transistor 10A and bipolar transistor 10B is individually determined or optimized for implementing a desired electrical characteristic of each transistor.
In the above mentioned semiconductor device of an insulation type composite element structure, however, the regions for element formation (i.e., islands) 25 are configured entirely the same. In other words, the thicknesses of the n.sup.+ layer 3 in both transistors 10A and 10B are the same. Further, it is not desirable to unnecessarily increase the depth of the p type well region in the transistor 10A because of its influence on the channel length, and the depth of p type base region 13 in the transistor 10B can't be made excessively deep because of its influence on the direct current amplification factor h.sub.FE. Therefore, the thickness of the n.sup.- layer 4 is determined depending on a transistor having a higher breakdown voltage of the transistors 10A and 10B, and as a result, the thickness of the n.sup.- layer 4 of another transistor with lower breakdown voltage becomes disadvantageously excessively thick.